Introduction

The basic MEK6800D1 board doesn't have a lot of user memory space. The basic offering by Motorola is only has one MCM6810L RAM (128 bytes) for user space ($0000₁₆ to $007F₁₆). There is also a MCM6810L RAM (128 bytes) for use by the MIKBUG/MINIBUG ROM, but should not be depended on for user space. To get more user space you need to purchase four more MCM6810 RAM chips. With a total of five MCM6810L RAMs, user program storage would be expanded to 640 Bytes ($0000₁₆ to $0280₁₆). The limited memory is understandable because the MEK6800D1 was only intended to be a trainer. But if your trying to do something really ambitious, like run the Resident Assembler or Editor, you need a lot more space.

But if you have bigger RAMs available, they probably won't plug directly in, due to pin out differences and address decoding, physical size, etc.. A way around this issue is with a "Daughter Board". A "Daughter Board" would contain all of the parts needed for a larger RAM expansion and would plug directly into the sockets intended for the MCM6810L RAMs.

The description below is how I solved the memory expansion issue using four MK4802 Static (2048 x 8) RAMS and two support chips. That gave me user space of 8,192 Bytes of memory, in the same effective space as the original 640 Bytes.

Note: I do not recommend this project for the inexperienced. The physical construction of the "Daughter Board" is pretty straight forward. However, I used #30 wire wrap wire to wire from the RAM socket pins directly to the pins on the MC6800. While the RAMs can be unplugged for the wiring, the MC6800 can not.

MEK6800-D1 Ram Expansion using MK4802 Static (2048 x 8) RAMS Physical Layout

The drawing on the right is a scaled (1" = 100 pixels) drawing of the memory expansion "Daughter Board". On the left and right of the "Daughter Board" are 12 pin 0.1" header sections. These header sectons mount on the bottom of the board and are positioned so that they will plug directly into the left side of the U3 IC socket and the right side of the U7 IC socket.

You should note that, the header sections are only for mechanically securing the "Daughter Board" to the MEK6800-D1 circuit board. There are no electrical connections to any of the pins on the header sections. While the holding force of one or two pins would not be sufficient to secure the "Daughter Board", 12 pins on each side would be sufficient.

At the time I built this board, I didn't have any IC sockets that matched the ICs. But I did have a bunch or 18 pin IC sockets. So I lined up a group of 12-18 pin sockets for the MK4802 RAMS and 2-18 pin sockets for the Address Decode logic ICs. The MK4802 RAM IC sockets are spaces 0.2" from each other. The space in between the MK4802 RAM and the Address Decode logic ICs is used for routing signal wires.

One of the initial issues is loading on the address and data busses. The MEK6800-D1 does not come with Address and Data buffers. If you intending to go off the board, a bi-directional buffer stage would be needed. However, I am building a "Daughter Board" that plug directly into the MEK6800-D1. So I am trying to minimize the chip count. The specification for the MC6800 CPU indicates that it is capable of driving 1 TTL load (1.6 ma, +130 pF) on the Address and Data bus output. As long as the Address and Data inputs to the MK4802 are sufficiently low, there shouldn't be a problem.

The schematic is split into three parts. The first part is the wiring for the MK4802 RAMs. The second is the Address Decode. And the third is the Power/Ground wiring. I could have fit it into one page, but it would be very cramped.

MK4802 RAMs

This drawing shows the RAM wiring. The Off-Page arrows on the left, A[15..00] and D[07..00], come directly from the MC6800 MPU. The wires from the MC6800 MPU are bundled and routed around the side of the MEK6800-D1 board to the "Daughter Board".

Address line A00 through A10 are applied directly to each MK4802 RAM IC, for a 2K Byte address block. Each 2K Byte address block is then selected by the CE (Chip Enable) signals created by the Control Signals and Address Decode logic. A total of 8K Bytes of user memory space is available.

When a RAM is not selected (CE = High) the Data signals (D00 to D07) are Tri-Stated. This allows the Data signals from all of the RAMs to be tied together without any issues.

Control Signals, Address Decode, and Power/Ground

This diagram shows the Control Signals, the Address Decode, and the Power/Ground wiring. I show the Power/Ground wiring separately to keep the signal wiring uncluttered. For the signal wires, on the other drawings, I used #30 wire wrap wire. But for the Power/Ground wiring I use a insulated #22 or #24 stranded wire.

Note the 0.1 µF capacitors (C1 through C6) next to each IC. These capacitors are soldered directly to the Power and Ground pins for each of the ICs. Their purpose is to help suppress any power transients or transients that were created by the ICs.

MEK6800-D1 Ram Expansion Timing