| Introduction |
| Address Range | Address Switch Setting | |||||
|---|---|---|---|---|---|---|
| 0000 to 1FFF | 1 | 0 | 1 | 0 | 1 | 0 |
| 2000 to 3FFF | 1 | 0 | 1 | 0 | 0 | 1 |
| 4000 to 5FFF | 1 | 0 | 0 | 1 | 1 | 0 |
| 6000 to 7FFF | 1 | 0 | 0 | 1 | 0 | 1 |
| 8000 to 9FFF | 0 | 1 | 1 | 0 | 1 | 0 |
| A000 to BFFF | 0 | 1 | 1 | 0 | 0 | 1 |
| C000 to DFFF | 0 | 1 | 0 | 1 | 1 | 0 |
| E000 to FFFF | 0 | 1 | 0 | 1 | 0 | 1 |
| Switch Numbers | 1 | 2 | 3 | 4 | 5 | 6 |
| 1 - "ON", 0 = "OFF" | ||||||
The EPA Associates 8K Memory Expansion, Rev. C board uses 64 - AM91L02APC Rams (1024 x 1 Static), several DS8833 Quad Tri-State Buffers for Address and Data I/O, and some descrete logic for upper address decoding. Initially I didn't have a schematic for it, but obtined one when some kind sole sent me a good PDF of the EPA Micro 68 computer. While there are a lot of ICs, it's a relatively simple circuit.
Page 1 contains the upper address decoder (A15 - A12) and drives the Chip Enables (CE) for each bank of memory chips The Dip Switch sets the base address of the memory unit, in 8K increments ($0000, $2000, $3000, etc... The table on the right describes the settings for the switches. Page 1 also contains the circuitry that generates the enable signals that control the bi-directional data in and out of the board.
Page 2 contains the lower Address Buffers (A11 - A0) and the Data Bus Buffers. While the data bus from the CPU is bi-directional, it needs to be split into two uni-directional buses. One for write data and one for read data. This is because the RAMs do not have bi-direction data ports.
Page 3 contains a single 1K x 8 Bank of memory. Overall, the board has 8 Banks. Bank A employs U1 through U8. Bank B employs U9 through U16. Etc.. For a total of 64 memory chips.
Page 4 contains the Power/Ground connections. Like Page 3, not all of the IC are shown descretly. Main power is supplied via the P1 connector and feeds a LM78H05 Voltage Regulator. The regulator requires 7.5 to 12 Volts DC input. Each of the ICs has an associated Bypass Capacitor. This capacitor should be installed as close to the Power/Ground pins of the IC as possible.
| Page 1 - EPA Memory Expansion - Address Decode/Buffer |
Note: The schematic, in the original documentation, has U69 labeled as a 74S123 (Dual Monostable). This is incorrect and should be a 74S138 (3 to 8 Decoder/Demux).
| Page 2 - EPA Memory Expansion - Data/Address Buffers |
| Page 3 - EPA Memory Expansion - Memory Bank, One of 8 (A thru H) |
| Page 4 - EPA Memory Expansion - Power and Ground |