Address Range |
Address Switch Setting |
0000 to 1FFF |
1 | 0 | 1 | 0 | 1 | 0 |
2000 to 3FFF |
1 | 0 | 1 | 0 | 0 | 1 |
4000 to 5FFF |
1 | 0 | 0 | 1 | 1 | 0 |
6000 to 7FFF |
1 | 0 | 0 | 1 | 0 | 1 |
8000 to 9FFF |
0 | 1 | 1 | 0 | 1 | 0 |
A000 to BFFF |
0 | 1 | 1 | 0 | 0 | 1 |
C000 to DFFF |
0 | 1 | 0 | 1 | 1 | 0 |
E000 to FFFF |
0 | 1 | 0 | 1 | 0 | 1 |
Switch Numbers |
1 | 2 | 3 | 4 | 5 | 6 |
1 - "ON", 0 = "OFF" |
The EPA Associates 8K Memory Expansion, Rev. C board
uses 64 - AM91L02APC Rams (1024 x 1 Static), several
DS8833 Quad Tri-State Buffers for Address and Data I/O, and
some descrete logic for upper address decoding. Initially I didn't have a schematic
for it, but obtined one when some kind sole sent me a good PDF of the
EPA Micro 68 computer. While there are a lot of ICs,
it's a relatively simple circuit.
Page 1 contains the upper address decoder
(A15 - A12) and drives the Chip Enables
(CE) for each bank of memory chips
The Dip Switch sets the base address of the memory unit, in
8K increments ($0000, $2000, $3000, etc... The table on the right describes the settings
for the switches. Page 1 also contains the circuitry that
generates the enable signals that control the bi-directional data in and out of the board.
Page 2 contains the lower Address Buffers
(A11 - A0) and the Data Bus Buffers. While the data bus from the
CPU is bi-directional, it needs to be split into two uni-directional buses. One for write data
and one for read data. This is because the RAMs do not have bi-direction data ports.
Page 3 contains a single 1K x 8 Bank of memory.
Overall, the board has 8 Banks. Bank A employs U1 through U8. Bank B employs U9 through U16. Etc..
For a total of 64 memory chips.
Page 4 contains the Power/Ground connections. Like Page 3, not all
of the IC are shown descretly. Main power is supplied via the P1 connector and feeds a
LM78H05 Voltage Regulator. The regulator requires 7.5 to 12 Volts DC
input. Each of the ICs has an associated Bypass Capacitor. This capacitor should be installed
as close to the Power/Ground pins of the IC as possible.
Page 1 - EPA Memory Expansion - Address Decode/Buffer |
Note: The schematic, in the original documentation, has
U69 labeled as a 74S123
(Dual Monostable). This is incorrect and should be a 74S138
(3 to 8 Decoder/Demux).
Page 1 - EPA Memory Expansion - Address Decode/Buffer
P1
J
6
R/W
17
∅2
10
VMA
14
13
15
11
10
12
5
6
4
2
3
1
DD
9
RD
7
DS8833
U76
R1
1KΩ
+
5
V
PU-R1
P1
33
A15
M
A14
N
A13
34
A12
14
13
15
11
10
12
5
6
4
2
3
1
DD
9
RD
7
DS8833
U72
5
6
SN74S04
U67
C
3
4
SN74S04
U67
B
1
2
SN74S04
U67
A
2
13
1
14
4
11
3
12
6
9
5
10
DIP Switch
9
10
11
8
SN7410
U66
C
1
2
13
12
SN7410
U66
A
D_Dis
Pg 3
3
4
5
6
SN7410
U66
B
11
10
SN74S04
U67
E
4
5
6
SN74S08
U65
B
1
2
3
SN74S08
U65
A
13
12
11
SN74S08
U65
D
10
9
8
SN74S08
U65
C
9
8
SN74S04
U67
F
R/W·∅2
To Pin 3 on all 64 RAMs
A
B
C
G1
G2A
G2B
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
1
2
3
6
4
5
15
14
13
12
11
10
9
7
S
N
7
4
S
1
3
8
U69
CE Bank A
CE Bank B
CE Bank C
CE Bank D
CE Bank E
CE Bank F
CE Bank G
CE Bank H
To Pin 13 on all 64 RAMs
A11
Pg 2
A10
Pg 2
13
12
SN74S04
U67
D
5
6
SN7407
U77-C
P1
12
Ena
R_Dis
Pg 3
Data Direction Control
Page 2 - EPA Memory Expansion - Data/Address Buffers |
Page 2 - EPA Memory Expansion - Data/Address Buffers
P1
32
D4
30
D5
L
D6
J
D7
14
13
15
11
10
12
5
6
4
2
3
1
DD
9
RD
7
DS8833
U71
D4
D4
D5
D5
D6
D6
D7
D7
P1
H
D3
K
D2
29
D1
31
D0
14
13
15
11
10
12
5
6
4
2
3
1
DD
9
RD
7
DS8833
U70
D0
D0
D1
D1
D2
D2
D3
D3
R_Dis
Pg 1
D_Dis
Pg 1
Data Direction Control
Data[7..0]
Pg 4
Data[7..0]
Pg 4
To All Memory
Banks A thru H
P1
35
A11
P
A10
R
A9
36
A8
14
13
15
11
10
12
5
6
4
2
3
1
DD
9
RD
7
DS8833
U73
A11
Pg 1
A10
Pg 1
A9
A8
P1
37
A7
S
A6
T
A5
38
A4
14
13
15
11
10
12
5
6
4
2
3
1
DD
9
RD
7
DS8833
U74
A7
A6
A5
A4
P1
39
A3
U
A2
V
A1
40
A0
14
13
15
11
10
12
5
6
4
2
3
1
DD
9
RD
7
DS8833
U75
A7
A6
A5
A4
PU-R1
Pg 1
Addr[9..0]
Pg 4
To All Memory
Banks A thru H
Page 3 - EPA Memory Expansion - Memory Bank, One of 8 (A thru H) |
Page 3 - EPA Memory Expansion - Memory Bank, One of 8 (A thru H)
8
A0
4
A1
5
A2
6
A3
7
A4
2
A5
1
A6
16
A7
15
A8
14
A9
DIN
11
DOUT
12
WE
3
CE
13
U1
AM91L02
R
A
M
1K
X
1
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
D7
D7
8
A0
4
A1
5
A2
6
A3
7
A4
2
A5
1
A6
16
A7
15
A8
14
A9
DIN
11
DOUT
12
WE
3
CE
13
U2
AM91L02
R
A
M
1K
X
1
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
D6
D6
8
A0
4
A1
5
A2
6
A3
7
A4
2
A5
1
A6
16
A7
15
A8
14
A9
DIN
11
DOUT
12
WE
3
CE
13
U3
AM91L02
R
A
M
1K
X
1
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
D5
D5
8
A0
4
A1
5
A2
6
A3
7
A4
2
A5
1
A6
16
A7
15
A8
14
A9
DIN
11
DOUT
12
WE
3
CE
13
U4
AM91L02
R
A
M
1K
X
1
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
D4
D4
8
A0
4
A1
5
A2
6
A3
7
A4
2
A5
1
A6
16
A7
15
A8
14
A9
DIN
11
DOUT
12
WE
3
CE
13
U5
AM91L02
R
A
M
1K
X
1
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
D3
D3
8
A0
4
A1
5
A2
6
A3
7
A4
2
A5
1
A6
16
A7
15
A8
14
A9
DIN
11
DOUT
12
WE
3
CE
13
U6
AM91L02
R
A
M
1K
X
1
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
D2
D2
8
A0
4
A1
5
A2
6
A3
7
A4
2
A5
1
A6
16
A7
15
A8
14
A9
DIN
11
DOUT
12
WE
3
CE
13
U7
AM91L02
R
A
M
1K
X
1
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
D1
D1
8
A0
4
A1
5
A2
6
A3
7
A4
2
A5
1
A6
16
A7
15
A8
14
A9
DIN
11
DOUT
12
WE
3
CE
13
U8
AM91L02
R
A
M
1K
X
1
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
D0
D0
A[9..00]
Pg 3
DI[7..0]
Pg 3
DO[7..0]
Pg 3
R/W·∅2
Pg 1
CE Bank A
Pg 1
R/W·∅2
Pg 1
CE Bank A
Pg 1
Page 4 - EPA Memory Expansion - Power and Ground |
Page 4 - EPA Memory Expansion - Power and Ground
P1
1
2
3
A
B
C
41
42
43
W
X
Y
+
C1
6.8 µF
VI
VO
GND
VR1
LM78H05
+5 Volts
+5V
Main +5 Volt Power Input
7.5 to 12 Volts DC Input on
Connector
VCC
10
VSS
9
U1 - AM91L02
+5V
C1
0.1 µF
VCC
10
VSS
9
U64 - AM91L02
+5V
C64
0.1 µF
+5 Volt Power For RAMs
U1 through U64 and
Associated Capacitors.
VCC
GND
14
7
U65 - SN74S08
+5V
C65
0.1 µF
VCC
GND
14
7
U66 - SN7410
+5V
C66
0.1 µF
VCC
GND
14
7
U67 - SN74S04
+5V
C67
0.1 µF
VCC
GND
14
7
U67 - SN74S04
+5V
C67
0.1 µF
VCC
GND
16
8
U69 - SN74S138
+5V
C69
0.1 µF
VCC
GND
16
8
U70 - DS8833
+5V
C70
0.1 µF
VCC
GND
16
8
U76 - DS8833
+5V
C76
0.1 µF
+5 Volt Power For Address/Data Buffers
U70 through U76 and
Associated Capacitors.
Note: IC location U68 is occupied
by the Address Dip Switch and does
not require a Bypass Capacitor.