Introduction

The circuits below are from the Motorola M6800 Microprocessor Application Manual.

M6800 Single Step Circuitry

When the Halt input is in the low state, all activity in the machine will be halted. This input is level sensitive. In the halt mode, the machine will stop at the end of an instruction, Bus Available will be at a one level, Valid Memory Address will be at a zero, and all other three-state lines will be in the three-state mode.

Transition of the HALT line must not occur during the last 250ns of Phase 1 (∅1). To insure single instruction operation, the HALT line must go high for one Phase 1 (∅1) clock cycle.

The circuit on the right, helps insure the proper conditions for single stepping. It is intended that switch S1 is a dual action momentary switch and S2 is a standard dual action switch. And that both switches are in their normally closed position. U1-6 (Step) and U1-11 (Halt/Run) will both be at a logic 0. This keeps U2 and U3 in a reset condition, forcing HALT to a logic 1.

The Timing Diagram below is helpful in understanding the Single Step mode.

• T0-T1 - Normal system clock.
• T1-T2 - The Halt/Run switch is moved to the Halt position.
• T2-T3 - The next rising edge of ∅1 will toggle U3A-Q to a "1". This will change HALT to a "0" and the system will go into a halt condition.
• T3-T4 - Indeterminate number of clocks.
• T4-T5 -
• T5-T6 -
• T6-T7 - Indeterminate number of clocks.
• T7-T8 -
• T8-T9 -
• T9-T10 -

M6800 DMA Circuitry

The term Direct Memory Access (DMA) is applied to a variety of techniques for speeding up overall system operation by loading and unloading memory faster than can be done using an MPU control program. DMA is often described as a means of allowing fast peripherals (perhaps another Microprocessor), to access the system memory without "bothering" the MPU. However, most DMA procedures do interfere with normal operation to some extent.

There are several ways that DMA can be accomplished. It just depends on how much you want the processor to be affected. Methods range from completly halting the processor, and accessing the data. To allowing external access during instruction cycles, reducing throughput or increasing execution time appreciably. Then there are methods that are somewhere in between the two. And that's what this section is about.

The specification for the M6800 requires two non-overlapping clocks (∅1 and ∅2). I'm not going to go into great detail, because you can simply read about the details in the M6800 Microprocessor Application Manual, starting in Chapter 4 - M6800 Famly Hardware Characteristics.