| Introduction |
This is a redraw of the schematic for the EPA Micro 68 Computer. I find that it is easier to understand when the functions are grouped properly. Plus, there is a space issue. The component size needs to be kept as small as possible, while still being perfectly readable. And, the drawing space is only 900 pixels wide by 600 pixels high. So the placement of each part is carefully done.
Printing - The diagrams below are dynamic drawings. They are drawn by Javascript when it loads into your browser. This may cause an issue with printing the drawings. To help solve that issue I have provided images of each page. The images are 900 pixels wide by 600 high (111 K) with a white, rather than a green, background.
| MPU Signal Description |
Proper operation of the MPU requires that certain control and timing signals be provided to accomplish specific functions and that other signal lines be monitored to determine the state of the processor. Listed below is a brief description of the signals that appear in the schematics.
Clocks Phase One and Phase Two (∅1, ∅2) - Two pins are used for a two-phase non-overlapping clock that runs at the VCC voltage level.
Address Bus (A0-A15) - Sixteen pins are used for the Address Bus. The outputs are Tri-State, output only, bus drivers capable of driving one standard TTL load and 130 pF. When the output is turned off, it is essentially an open circuit. This permits the MPU to be used in DMA applications.
Data Bus (D0-D7) - Eight pins are used for the Data Bus. It is Bi-Directional, transferring data to and from the memory and peripheral devices. It also has Tri-State output buffers capable of driving one standard TTL load and 130 pF.
Halt - When this input is in the low state, all activity in the machine will be halted. This input is level sensitive. In the halt mode, the machine will stop at the end of an instruction,. Bus Available will be at a one level. Valid Memory Address will be at zero, and all other three-state lines will be in the three-state mode.
Three-State Control (TSC) - This input causes all of the address lines and the Read/Write line to go into the off or high impedance state. This state will occur 500 ns after TSC = 2.4V. The Valid Memory Address and Bus Avaulable signals will be forced low. The data bus is not affected by TSC and has its own enable (Data Bus Enable). In DMA applications, the Three-State Control line should be brought high on the leading edge of the Phase One Clock. The ∅1 clock must be held in the high state and the ∅2 in the low state for this function to operate properly. The address bus will then be available for other devices to directly address memory. Since the MPU is a dynamic device, it can be held in this state for only 5.0 µs or destruction of data will occur in the MPU.
Read/Write (RD/WR) - This TTL compatible output signals the peripherals and memory devices whether the MPU is in a Read (high) or Write (low) state. The normal standby state of this signal is Read (high). Three-State Control going high will turn Read/Write to the off (high impedance) state. Also, when the processor is halted, it will be in the off state. This output is capable of driving one standard TTL load and 130 pF.
Valid Memory Address (VMA) - This output indicates to peripheral devices that there is a valid address on the address bus. In normal operation, this signal should be utilized for enabling peripheral interfaces such as the PIA and ACIA. This signal is not three-state. One standard TTL load and 30 pF may be directly driven by this active high signal.
Data Bus Enable (DBE) - This input is the three-state control signal for the MPU data bus and will enable the bus drivers when in the high state. This input is TTL compatible, however in normal operation, it would be driven by the phase two clock. During an MPU read cycle, the data bus drivers will be disabled internally. When it is desired that another device control the data bus such as in Direct Memory Access (DMA) applications, DBE should be held low.
Bus Available (BA) - The Bus Available signal will normally be in the low state, when activated, it will go to the high state indicating that the microprocessor had stopped and that the address bus is available. This will occur if the Halt line is in the low state or the processor is in the WAIT state as a result of the execution of a WAIT instruction. At such time, all three-state output drivers will go to their off state and other outputs to their normally inactive level. The processor is removed from the WAIT state by the occurrence of a maskable (mask bit 1 = 0) or nonmaskable interrupt. This output is capable of driving one standard TTL load and 30 pF.
Interrupt Request (IRQ) -
This level sensitive input requests that an interrupt sequence be generated within the machine. The
processor will wat until it completes the current instruction that is being executed before it
recognizes the request. At the time, if the interrupt mask bit in the Conditional Code
Register is not set, the machine will begin an interrupt request by setting the interrupt mask
bit high so that no further interrupts may occur. At the end of the cycle, a 16-bit
address will be loaded that points to a vectoring address which is loaded at these
locations FFF8 and FFF9. An address loaded a these locations causes the MPU to branch to an
interrupt routine in memory.
The Halt line must be in the high state for interrupts to be reognized.
The IRQ has a high impedance pullup device internal to the chip; however a 3 KΩ external resistor to VCC should be used for Wire-OR and optimum control of interrupts.
Reset - This input is used to
reset and start the MPU from a power down condition, resulting
from a power failure or an initial
start-up of the processor. If a positive edge is detected on the input, this wil signal the
MPU to begin the restart sequence. This will start execution of a
routine to initialize the
processor from its reset condition. All the higher order address lines will be forced high.
For the restart, the last two (FFFE, FFFF) locations in memory will
be used to load the program
that is addressed by the program counter. During the restart routine, the interrupt mask bit
is set and must be reset before the MPU can be interrupted by
IRQ.
Figure 4 shows the initialization of the microprocessor after restart. Reset must be held low for at least eight clock periods after VCC reaches 4.75 volts. If Reset goes high prior to the leading edge of ∅2, on the next ∅1 the first restart memory vector address (FFFE) will appear on the address lines. THis location should contain the higher order eight bits to be stored into the program counter. Following, the next address FFFF should contain the lower eight bits to be stored into the program counter.
Non-Maskable Interrupt (NMI) - A low-going edge on this input requests that a non-mask interrupt sequence be generated within the processor. As with the Interrupt Request signal, the processor will complete the current instruction that is being executed before it reccognizes the NMI signal. The interrupt mask bit in the Condition Code Register has no effect on NMI.
| Table 1 - Memory Map for Interrupt Vectors | ||
|---|---|---|
| Vector | Description | |
| MS | LS | |
| FFFE | FFFF | Restart |
| FFFC | FFFD | Non-Maskable Interrupt |
| FFFA | FFFB | Software Interrupt |
| FFF8 | FFF9 | Interrupt Request |
The Index Register, Program Counter, Accumulators, and Condition Code Register are stored away on the stack. At the end of the cycle, a 16-bit address will be loaded that points to a vectoring address which is located in memory locations FFFC and FFFD. An address loaded at these locations causes the MPU to branch to a non-maskable interrupt routine in memory.
NMI has a high impedance pullup resistor internal to the chip; however a 3KΩ external resistor to VCC should be used for Wire-OR and optimum control of interrupts.
Inputs IRQ and NMI are hardware interrupt lines that are sampled during ∅2 and will start the interrupt routine on the ∅1 following the completion of an instruction.
Figure 5 is a flow chart describing the major decision paths and interrupt vectors of the microprocessor. Table 1 gives the memory map for interrupt vectors.
| EPA Micro 68 Block Diagram |
The heart of the EPA Micro 68 Computer is shown on Page 1 of the schematic. It includes the Clock, CPU, MIKBUG ROM/RAM. The MIKBUG ROM/RAM block actually consists of a single MC6830 ROM ($E000) and a MC6810 RAM (128 Bytes at $A000). Normally, the MIKBUG ROM/RAM components are not installed or used by the overall EPA Micro 68 system.
| EPA Micro 68 MPU, ROM, and RAM - Page 1 |
This page shows the basic 6800 CPU (U11) with an associated ROM (U9) and RAM (12). This ROM (MC6830) and RAM (MC6810) are not normally used with the EPA Micro 68 and will just be empty 24 pin sockets. You can see that this section of the EPA Micro 68 very closely matches the Motorola MEK6800D1 Evaluation Module.
The intent of U9 and U12 is for the Motorola MCM6830L7 MIKBUG/MINIBUG ROM/RAM, which is described in the Motorola Engineering Note 100. Using the MIKBUG/MINIBUG ROM/RAM is beyond the scope of this section. Just note that it can possibly be use.
| EPA Micro 68, User Ram 5 x 128 Bytes - Page 2 |
This page shows the user memory space. The EPA Micro 68 really only comes with one MCM6810 in place at U16. If you want more than 128 Bytes of memory, you will need to add extra MCM6810s. The schematic shows the full compliment of MCM6810s. The full compliment will provide you with 640 Bytes (5 x 128) of user memory.
| EPA Micro 68, LED Display Interface - Page 3 |
| EPA Micro 68, Keypad Interface - Page 4 |
| EPA Micro 68, Address/Data Buffer, Keyboard Monitor ROM - Page 5 |
There were a few errors in this section of the original schematic.
- In the original schematic, on the left side of the 8T28s used for the Data Buffer, there are alternate listings of U6 and U7. But the 8T28 is drawn as a single whole unit. Either the alternate listings of U6 and U7 are incorrect, or the 8T28s are drawn incorrectly. I choose to think that the 8T28s are drawn correctly and that the alternate listing of U6 and U7 is incorrect.
- In the original schematic, the enables on U6-15 and U7-15 show a signal named VMA·∅2·R/W, but that signal doesn't show anywhere else on the drawing. That signal turns out to be the output of U15-8, which is a SN7430 8-Input NAND gate that drives the monitor PROM chip select.
| EPA Micro 68, Power/Ground - Page 6 |
This page contains all of the Power/Ground tie-ups, except for local pull-up and pull-down resistors and grounds. The capacitors on each IC are for noise reduction. I named them CU1 to CU28 because they are not on the original schematic, even though they actually exist. They are all listed here because, it is common practice to locate all Power/Ground specifications to the final page of a multi-page drawing.