Introduction

This page shows how to add memory to your keyer. The first one includes a keyer that connects directly to the memory section. It uses three signal lines (clock, data out, and data in) to communicate with the memory. This means that the same clock that runs the keyer also runs the memory.

Poor Man's CW Memory - Eric Unruh, WB0RYN

This design was published by Eric Unruh, WB0RYN, in the June, 1979 issue of 73 Magazine. Although in the article Eric credits Elmer Watts, K0HAO, with the original idea.

This design can be used with any key or keyer. It is just a add-on that can be used with whatever key or keyer you have. Hookup is relatively simple. You just add the CW Memory in between your keying device and your transmitter. You plug your keying device into J1. Then you take the output of the add-on memory and connect it to your transmitter. A switch is available (S2) for switching out the memory, when the memory isn't needed.

Note: I did not include a keying interface. However, this is needed depending on what kind of keying your transmitter requires (Grid Block or Cathode keying).

Operation is simple. Turn on the Memory/Key switch (S2) to the Memory position, turn the Read/Write switch (S1) to the Write position, turn the Audio switch on (S5), Reset the memories (S4), and key in the message you want. When you're finished, switch the Read/Write switch back to Read (S2) and Reset the memories (S4). Your message should play back.

Erasing - With the Erase switch off, the Inverter U8-A (Pin 2) is normally "high", which then holds the negatice side of C1 "low". This then allows the Clock Oscillator (U6) to run at normal speeds. If the Erase switch is closed, negatice side of C1 goes "high" allowing the Oscillator to run at a high speed (~200KHz).

This next page contains the Sidetone Oscillator and the Power/Ground wiring. The sidetone can be made adjustable by replacing R9 (1MΩ) with a trimmer around the same value. Initially it appears that there is no keying for the sidetone. Keying the sidetone is accomplished by grounding pin 1 of the NE555. This is shown in the Power/Ground wiring. The sidetone can be completely disabled with S5.

The 0.01 µF bypass capacitors on each IC were added by me. It is good TTL design practice to add bypass capacitors to each IC. This helps to keep switching transients from one IC getting to any other IC and degrading operation. Note that the NE555s use a much higher value (47 µF) for a bypass capacitor. This is because some 555s can generate a lot of trash on the power bus.

Build a CW Memory - Larry Kasevich WA1ZFW

This design records what an operator actually sends with his key.

This drawing below is for the Memory Address Counter, Chip Enable Decode, and Ram storage of the CW Memory. You may notice the odd addressing on the Rams. I drew this schematic, trying to keep the authors original wiring, pin for pin. While the Address Counter (U5-CD4040) output lines go nicely from A[00] to A[11], the addresses at the Rams are not in order. I assume that this is due to the PC layout. At the Ram, the ordering of the addresses doesn't really matter.

Bug Key With 528-Bit Memory - Graham Moore, G4DML

This design records what an operator actually sends with his key.

Circuit Description

The keyer consists of a standard "el-bug" circuit around U3, gated to both the keying relay, RLA, and to the recirculating shift register memory. This is made up of eight 4031 64-stage static shift registers, designed so that the data once entered shifts continuously around the loop formed by thes ICs and their associated circuitry.

Both keyer and memory are clocked by the continuously variable CMOS oscillator formed by U1. The clock drive to the shift register can be disabled so that the keyer can be used as a standard el-bug without storage. This method of storing the data was chosen as it alleviates the problem of generating the address encoding and decoding that would be required if RAM type memory was used.

The data is read in purely as a serial data stream and read out in exactly the same way; note however that the data is stored inverted in order to simplify start and stop bit identification. In order to locate the start of the message a synchronising pulse of eight blanks is left at the beginning of any data entry. The circuitry that detects this pulse, U8 and U10, is also used at the other end of the memory, U9 and U11, to enable any large blanks in the stored message to be run through at very high speed. This is done automatically switching oscillator speeds by U2 and U7 when more than eight blanks are detected by U9 and U11. When the first data bit is detected by U8 and U10 the clock is switched back to normal speed and keying continues..

Functional Description

MEMORY ON/OFF:	This enables the clock to the recirculating memory. When in the OFF position the keyer can be used as a normal el-bug with no storage facility.
LOAD:	When used in conjunction with MEMORY ON, any keyed data is loaded into memory. The clock is automatically disabled when no keying is present so as not to run through the memory filling it with blanks. Note that this switch must be in the LOAD position to enable the paddle to operate the keyer.
CLEAR:	When used in conjunction with MEMORY ON the entire memory space is cleared in approximately two seconds. It must be pressed and held down until the memory FULL LED extinguishes at the start of every load cycle.
READ:	In this position with the memory switched ON, information stored in the memory will be read out to the keyed relay and DATA LED.
DATA and FULL LEDs:	These two indicators are included on the keyer so that an eye can be kept on the operation of the unig. The DATA LED indicates the information being sent to the keying relay. The FULL LED indicates when there are eight more empty memory locations left. Normally unless the data entry can be completed by this time, the memory will then have to be cleared and a shorter message input.

The SPEED control is self-explanatory, allowing datra to be keyed in at one speed and output at another. A rate of 400 letters per minute is the normal speed used for m.s. contacts.