Heathkit HD-1410 |
The Heathkit HD-1410 Features |
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Self-completing Dots and Dashes |
Dot and Dash Memories |
Iambic Operation |
Dot and Dash Insertion |
Built-in Paddles |
5-50 WPM Speed Range |
Built-In Sidetone Oscillator and Speaker |
Headphone Jack that silences the Speaker |
Solid-state Output. |
As I mentioned in the introduction to this section, the Heathkit HD-1410 was the first keyer that I ever owned. Since it was also my only keyer, I really didn't have anything to compare it to. So I thought it was great. Some hams didn't like the built-in Paddles. They complained that it was hard to get the same response from both paddles. Personally, I found the paddles very easy to work with and easy to set up. All you need is a little patience.
While the HD-1410 is capable of Iambic Operation, I never bothered to use that feature. I researched it a bit, and tried operating the keyer Iambicly, but found that all I did was create a bunch of errors.
Note that, some of the descriptions below are similar to versions of the explanation provided by Heathkit in their manual.
Also note that, in my schematics, integrated circuits that contain multiple logic elements, like the SN7400 which contains four 2-Input NAND gates, may not have the same element designator as the original original schematic. Where necessary, this had been adjusted for in the explanations. However, the integrated circuit pin numbers do match the original schematic.
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Printable Images of each Schematic Page
- Page 1 - Bit Memories/Reset, Clock Enable
- Page 2 - Clock and Bit Generator
- Page 3 - Side Tone, TX Keying
- Page 4 - Power Supply
Further, for Reference Designators, Heathkit used "IC". Whereas, I use "U".
The schematic for the Heathkit HD-1410 keyer is below. Due to available space, and the fact that I don't like cluttered schematics, I split the schematic into four drawings. I tried to include everything that the original schematic had, but then the drawings start to get cramped and cluttered. The Block Diagram, below, shows how the schematic was divided up.
Page 1 - Next-Bit Memories" (NBM), Present-Bit Memories (PBM), and Reset Circuitry |
There are two "Next-Bit Memories". One for Dots, composed of U1A and U2A. And one for Dashes, composed of gates U1B and U2B. Each pair of gates is cross-coupled to form an S-R (Set-Reset) flip-flop. Since their operation is similar, only the Dash NBM will be discussed.
When no bit is being sent, U2D‑8 is a 1, since the clock (CLK_Q2) is a 1. The Dash NBM is in the reset condition, with U2B‑6 at a 1 and U1B‑3 at a 0. This 0 is applied to U3B‑4. Therefore, U3B‑6 is a 1. (Similarly, U3A‑8 is also a 1.) When the Dash paddle is keyed, U1B‑2 is grounded momentarily through the paddles contacts. This causes U1B‑3 to go a 1. U2B‑4 and 5 are both at a 1, so U2B‑6 goes to a 0. This 0 is applied to U1B‑1 and holds U1B‑3 at a 1 after the paddle is released. U3B now has a 1 on all three inputs, so pin 6 is a 0. This 0 is applied to U1C‑13, and U1C‑11 goes to a 1. U1D‑8 goes to a 0, and the bit generator begins to form a Dash (since U4B‑2 is at a 1).
Note that U3B and U3A form a S-R flip-flop which, depending on its state, causes the Bit Generator to form Dots or Dashes as described in the section on bit generation.
At the end of a bit, whether Dot of Dash, the PBM must assume the state of the next bit to be sent. This is accomplished by the Reset Circuitry. U5C, U2B, resistor R3, and capacitor C1 form the Dash Reset circuit. (The Dot Reset circuitry is composed of U5D, U2A, resistor R4, and capacitor C2 operates the same.) Iambic operation requires that if both paddles are closed, or if the Dot paddle is keyed during a Dash bit, or the Dash paddle is keyed during a Dot bit, the next bit must be opposite to that being sent.
Assume a Dot is being sent. This means that U3A‑8 is 0 and U3B‑6 is 1. This 1 is applied to U5C‑9 and holds U5C‑10 at a 0. The trailing edge of the clock pulse occurring a the end of the Dot bit mark takes U3C‑12 at a 0. At this time, U5D has both inputs at a 0, and U5D‑13 goes to a 1. This enables U2C for the next clock pulse, which occurs at the end of the Dot bit. The leading edge of this clock pulse takes U2C‑11 to a 0. This will reset the Dot NBM unless the Dot paddle is still closed. If the Dash paddle has not been closed, then there is a 0 on U3B‑4 which holds U3B‑6 at a 1, and the PBM cannot change state. Thus the next bit will be another Dot. If, however the Dash paddle had been keyed sometime during the Dot bit, then U3B‑4 will be high. When U2C‑11 goes to a 0, U3A‑10 goes to a 0, and U3A‑8 goes 1. Then U3B has all inputs at a 1 so U3‑6 goes to a 0 and holds U3‑8 at a 1 following the clock pulse. On the trailing edge of this clock pulse, the Bit Generator begins a Dash, since U4‑2 is a 1.
A necessary delay is provided by R3 and C1. Recall that when the PBM changed state, U3‑6 went low on the leading edge of the clock pulse. U3‑12 does not go to a 1 until the trailing edge of the clock pulse. Were it not for the delay, U2‑9 and 10 would be at a 1, and the 0 on U2‑8 would remove the Dash from this memory if one were stored there.
Page 2 - Clock and Bit Generator |
The clock consists of transistors Q1, Q2, and their associated circuitry. When CLK_ENA is high, the clock (CLK_Q2) is disabled. Capacitor C3 charges through diode D1 and biases Q1 off. With Q1 off, the base of Q2 is high. Therefore, Q2 is also off and the clock output is low. Note that the high on CLK_ENA is also applied through D2 to U4A pin 5. When CLK_ENA goes low (bit being sent), U4A changes state. D1 is then back-biased and C3 begins to discharge through resistor R9, Speed control R101, and resistor R11. When its voltage drops to the base potential of Q1, Q1 begins to turn on. The collector of Q1 and the base of Q2 begin to go less positive and turn on Q2. As Q2 turns on, its rising collector potential is coupled through capacitor C4 to the base of Q1 and turns it on harder. Thus the condition is regenerative and happens very quickly.
The Bit Generator is composed of U4A and U4B, and U3C. In the resting condition, U4A and U4B are reset (Q outputs are 0). The 1 on U3C‑1, 2, and 13 causes U3C‑12 to be a 0 (Key-Up). If U4B‑2 is a 0, U4B cannot change state. The waveform in Figure 10 show how Dots and Dashes are formed. Note that if U4B‑2 is 0, Dots are generated; if it is a 1, Dashes are generated.
Page 3 - Side Tone Oscillator, Transmitter Keying Circuit |
The Sidetone Oscillator is made up of U5A and B, which are cross-coupled to form an astable multivirator. It is enabled when U5B Pin 6 goes to a 0. Its output is coupled to Q3, which drives the speaker.
When U3C‑12 (Page 2) goes to a 1 (mark condition), it turns on the Darlington pair, transistors Q6 and Q7, which will key positive lines to ground. Transistor Q4 also turns on, thus turning on transistor Q5 and keying negative lines to ground through the power supply and resistor R25. Note that no more than approximately 10 mA may be keyed by this circuit since it is a constant sink which limits at 10 mA. Diodes D4 and D5 isolate the two sections.
The Keyer Output line is bipolar and can handle positive keyed lines (Cathode Keying) as well as negative keyed lines (Grid-Block Keying) that are common with vacuum tube transmitters. This seems to work nicely, but it has been suggested that three of the output transistors could be replaced with more modern devices with better ratings.
- Q5 could be replaced with a with an NTE288 transistor (PNP - 300 Volt, 500 mA, 625 mWatt)
- Q6 and Q7 with a pair of NTE287 transistors (NPN - 300 Volt, 500 mA, 625 mWatt)
Page 4 - Power Supply and Power Wiring |
The Power Supply is conventional series regulated bridge circuit that supplies +5 volts. Diode D6 protects the power supply against reversed battery polarity.
The supply can be configured to operate from 240 Volts AC, 120 Volts AC, or 12 Volts DC. On 120 Volts AC, the two primaries are run in Parallel. On 240 Volts AC, the two primaries are run in Series. The appropriate fuse should be used based on the supply voltage. The power and ground wiring is included for the ICs on page 1, 2 and 3
Schematic Notes |
1. | Component numbers are in the following groups. 1-99 parts mounted on the circuit board 101-199 Parts mounted on the chassis. |
2. | All Resistors are 1/4 watt unless marked otherwise. Resistor values are in Ohms (K=1000). |
3. | Voltages may vary +/-20%, |
4. | All capacitor values are in MicroFarads (µF) |
5. | Refer to the chassis photographs and circuit board X-Ray views for the physical location of parts. |
6. |
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7. |
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8. |
G connection that is soldered. |
9. |
circuit board. |
10. | → Indicates clockwise rotation of control shaft. |
11. |
RF RF |
12. |
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13. | L - Low level logic. Approx. 0.09V |
14. | H - High level logic. Approx. 4.0V |
15. | * This symbol indicates the voltage depends on the settings of control R17 |
16. | The waveforms were taken under the following conditions:
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17.** | R9 = 5600Ω for 10 to 60 words per minute speed. R9 = 10KΩ for 10 to 35 words per minute speed. |
Keyer Timing |
The image below is redrawn from the Verilog simulation of the HD-1410 keyer. I redrew it because it allows me to annotate easier. The times, "T0 to T20", are arbitrary times and are applicable at any speed. They are only used as event markers.
The image shows the basic operation of the HD-1410 logic sending the letters "A", and "B". The keyer controls the length of the dots, dashes, and space between letter elements. However, space between letters and words is up to the keyer operator.
In the simulation, the top two traces are the Dot and Dash Paddle input. The paddle inputs are normally "high" and are taken "low" when a paddle is closed. The arrows from the first dot (T1) show that the dot paddle closure sets the "Dot_Set" register, which then sets the "Clk_Ena". A short time after the dot paddle is closed, and released, the dash paddle is closed (T2 ≬ T3). As long as the dash paddle is closed before the space following the dot is complete, a dash will be produced and the "Clk_Ena" will continue to be active. The dash is self completing so the dash paddle can be released before the dash is completed.
Below the paddle inputs is the CW_Out signal. This signal happens before the Keyer Output Circuit on Page 2. When the CW_Out signal is "high" the transmitter is being keyed.
The waveforms shown here, only deal with one method of sending. I also simulated "squeeze" keying and verified that an extra dot can be generated, if the paddles are not operated properly. There is no fix for the extra dot, but there doesn't really need to be one. Many of the other keyers included in this section, have the same issue.
HD-1410 Modifications |
Keyer Speed
On page 2 of the schematic, is the Keyer Clock. The keyer speed, in WPM (Words Per Minute), is controlled by R9. If you use 5,600Ω for R9, the speed range should be from 10 to 60 WPM speed. But it may be difficult to adjust the speed, due to the wide range. To reduce the WPM range to 10 to 35 WPM, R9 can be changed to a 10KΩ resistor.
That suggestion works fine but another suggestion is to add a 5.6KΩ resistor in series with R9 and then shunt Speed Control, R101, with a 33KΩ resistor. That should change the speed range to 8 to 35 WPM.
Modifications For Use With Ten-Tec, Triton And Rigs With Similar Keying
These modification are described in the Service Bulletins listed below. But I thought a schematic of the modification would be nice.
Bulletin No: HD-1410-1, Part A - If you match this drawing up with the Keyer Output Circuit, on page 2, you should notice that R27 and D5 are replaced with 0Ω resistors (or wire jumpers). Using a 0Ω resistor in R27 shorts the base of Q7 to ground, effectively, removing Q7 from the circuit. Using a 0Ω resistor in D5 eliminates the 0.7 VDC offset from ground.
Bulletin No: HD-1410-1, Part B - If the keyer needs to be used with Cathode OR Grid-Block keyed rigs, the modifications in the drawing should be made, and used for Grid-Block keyed transmitters "only". For rigs that employ a positive key line, and solid state keying circuits (Cathode keying), the "Ext. Key" jack is repurposed.
The modification consists of mounting a terminal strip (three terminals with center terminal ground) below the "Ext. Key" jack. Mount a 4,700Ω resistor across pins 1 and 3. Then mount a MPSA20 transistor on the terminal strip with:
- Base - Connected to lug 1
- Emitter - Connected to lug 2 (center)
- Collector - Connected to lug 3
Service Bulletins |
April 17, 1975 | |
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HD-1410 Electronic Keyer | Bulletin No: HD-1410-1 |
Modifications For Use With Ten-Tec, Triton And Rigs With Similar Keying Requirements | |
It has been found that the Ten-Tec Argonaut and Triton keyin circuits
require that the key-line be brought to within a few tenths of a volt of
ground to operate properly, Either of the following modifications to the
HD-1410 will allow it to be used with the above units:
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Keyer Keys Continuously Or Erratically | |
Problems with RF causing the keyer to key continuously or erratically, particularly when using long wire or random length antenna systems, can be eliminated by connecting a .001 µF disc ceramic across the keyer output jack. | |
Intermittent Sidetone | |
In some units, if the "tone" control is turned fully clockwise [low frequency end], the sidetone will be intermittent. Turning the pot slightly counterclockwise will eliminate the condition. |
May 20, 1975 | |
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HD-1410 Electronic Keyer | Bulletin No: HD-1410-2 |
Service Guide | |
The following is a step by step procedure for servicing the HD-1410 Keyer: | |
Equipment Needed: 1 VTVM [Not a VOM or DVM] Set VTVM as follows: To read DC + Voltage |
Set controls on HD-1410 as follows: AC Switch - ON Speed - Full CCW Volume - 1/4 CW |
C A U T I O N When making voltage checks in the unit, be very careful where the probe is touched as 110V AC voltage is present also.
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May 20, 1975 | |
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HD-1410 Electronic Keyer | Bulletin No: HD-1410-3 |
Keyer Keys Continuously Or Erratically | |
In the next run, a .005MFD [5000pF, PN 21-57] will be added across the Keyer output jack. This supersedes the information in Bulletin No: HD-1410-1 | |
26, 1976 | |
HD-1410 Electronic Keyer | Bulletin No: HD-1410-4 |
No Dots Or Dashes | |
If the unit has no dots or dashes output, but has a tone in the "hold" mode, check the
installation of Q2. The customer apparenly tries to twist the transistor so that the
flat of the transistor will align with the flat screened on the board. This will cause
the base & collector leads to short. The manual is being changed to clarify the installation of this transistor. | |
JUNE 24, 1976 | |
HD-1410 Electronic Keyer | Bulletin No: HD-1410-5 |
RFI | |
RFI in the keyer coming through the power supply can be eliminated by installing two .005UFD/1.6KV capacitors [PN 21-44] across the AC line to the ground. | |
July 9, 1976 | |
HD-1410 Electronic Keyer | Bulletin No: HD-1410-6 |
Wrong Type Of Round Knob | |
Some kits were shipped with round knobs [PN 462-932] that will not accept the knob bushing. Although these knobs will fit onto the control shafts, the knob pointer may not align properly. | |
September 23, 1977 | |
HD-1410 Electronic Keyer | Bulletin No: HD-1410-7 |
Keyer Locks On Some Bands | |
++++Info not yet available++++ | |
September 23, 1977 | |
HD-1410 Electronic Keyer | Bulletin No: HD-1410-7 |
Keyer Locks On Some Bands | |
++++Info not yet available++++ | |
July 24, 1978 | |
HD-1410 Electronic Keyer | Bulletin No: HD-1410-8 |
No Dashes; Tone And Dots Okay | |
Check for a possible foil bridge between pins 8 and 9 or between pin 8 and ground of the Dash Reset circuit, IC2 [PN 443-1]. The bridge is usually too small to see without a magnifier. The bridge usually can be removed by scraping the area around pins 8 and 9 with a knife or other similar object. | |
May 8, 1980 | |
HD-1410 Electronic Keyer | Bulletin No: HD-1410-9 |
Sidetone Not Loud Enough | |
++++Info not yet available++++ |