Memory Keyer - Barry L. Ives, AI2T

Printable Images of
each Schematic Page
• Page 1 - Keyer
• Page 2 - Memory
• Page 3 - Power/Ground

While this keyer is attributed to Barry L. Ives, AI2T, I found out that this keyer was published in the Winter 1986 issue of QRP Quarterly. However, all I have been able to find on-line is this JPG image. I find that the keyer to be very simple. Not only is the keyer section simple, I think i is a very clever use of a Shift Register.

AI2T Memory Keyer, Keyer Section, Page 1

If all you needed was a simple keyer, the Keyer section drawn below is all you need. Note that the power and ground tieups, are on page 3.

AI2T Memory Keyer, Memory Section, Page 2

The next drawing is for the addition of memory to the keyer above. While this design seems to be simple, there are several questionable areas.

There are three switches that control the memory: S1 (Load 1), S2 (Load 2), and S5 (Program). S1 and S2 should be push button switches while S5 should be a toggle switch. When S5 is closed, momentarily activating S1 or S2 will allow one of the rams to be loaded. With S5 open, momentarily activating S1 or S2 will play back the message stored in one of the rams.

Note that S1 and S2 directly clear or set the counters, respectively. The counter's clear signal overrides load, data, and count inputs. This means that, when S1 is pressed, the counter will not start counting until it is released.

The counters (U4-U6) form a 12 bit address bus. The lower 10 address bits (A0-A9) are used to directly address the rams. The inverse of address bit 10 (A10) is used as the STOP signal. When A10 is a "1", the clock that drives the counters is disabled (U8D), preventing the counters from incrementing. The STOP signal (the inverse of A10 (U9B)) is used to enable the RAM Chip Enable (U1-CE and U2-CE) signals. Only one Chip Enable should be active, "0", at a time.

AI2T Memory Keyer, Power/Ground, Page 3

This next diagram is the Power/Ground wiring for the Memory Keyer. If you only wanted to try out the keyer, U3, U9, and U7 are the only ICs you need. I added extra bypass capacitors to the Power/Ground detail to help increase the noise immunity. Note that U7, the NE555 timer, has a extra large capacitor. These timers have a tendency to produce lots of noise on the power bus.

Note, there are a couple of oversights in the Original Schematic.

• In the original schematic (Page 1) U9D Pin 11, which drives the output keying transistor Q1 through a 470Ω resistor, is drawn as a NAND gate. That is correct. However, U9D is labeled as a SN74LS08. It should be labeled as a a SN74LS00.
• Two of the LEDs are show wired incorrectly. LED1 and LED2 have their Cathodes going to a signal, RUN 1 STOP and RUN 2 STOP. Their Anode's go to ground, through a 470Ω resistor. Unless the signals on the Cathodes go negative, the LEDs will never light. The resistors need to be tied to +5 volts, instead of ground, in order for the lights to operate when the signal goes active (low).
• There are 5 switches in the circuit, S1, S2, S4, S5, and S6. Reference designator S3 is missing.
• None of the resistors and capacitors have reference designators. I assigned them as I saw fit.