Mini-MOS Keyer

Below is the schematic for the Mini-MOS Keyer that was published in the August 1976 issue of 73 Magazine written by Erich A. Pfeiffer, WA6EGY.

In that original article, there are two small errors in the output circuit for the Sidetone Oscillator output. I looked for an update in the 73 Magazine. I didn't find one, but that doesn't mean there wasn't one. I just failed to locate it.

Anyway, the Emitter of Q2 and the Positive (+) side of the 1.5 Volt Battery (B2) are shown going to −VDD. But there is no −VDD. Those two connections should really be listed as −VSS. I corrected this in the drawings below.

I am not going to say much in the line of circuit description. The original article does a pretty good job of that.

Mini-Mos Schematic, Page 1
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2
1
8
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6
5
4
3
2
1
A
B
C
D
A
B
C
D
Erich A. Pfeiffer, WA6EGY
Title
Key Logic
Size
B
Document Number
73 Mag, Aug 1976
Rev
None
Date:
3/7/2020
Sheet 1 of 3
DOT
PADDLE
-VSS
C1
0.001uF
-VSS
R1
270KΩ
+VDD
DASH
PADDLE
-VSS
C2
0.001uF
-VSS
R2
270KΩ
+VDD
6
5
4
CD4011
U1
A
8
9
10
CD4011
U1
B
Next-Dot Memory
6
5
4
CD4081
U2
A
8
9
10
CD4081
U2
B
1
2
3
CD4011
U1
C
13
12
11
CD4011
U1
D
Next-Dash Memory
1
2
3
CD4081
U2
C
13
12
11
CD4081
U2
D
S
R
D
Q
Q
3
5
6
4
1
2
CD4013
U3
A
-VSS
U3A_Q
P2-D6
U3A_QN
P2-6D
Present-Dot
Memory
S
R
D
Q
Q
11
9
8
10
13
12
CD4013
U3
B
-VSS
Present-Dash
Memory
U3B_QN
P2-6B
PDM_CLK
P2-4B
1
2
3
CD4081
U4
A
OSC_ENA
P2-A8
Mini-Mos Schematic, Page 2
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1
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1
A
B
C
D
A
B
C
D
Erich A. Pfeiffer, WA6EGY
Title
Clk, Dot/Dash Timing, Tone Gen.
Size
B
Document Number
73 Mag, Aug 1976
Rev
None
Date:
3/7/2020
Sheet 2 of 3
OSC_ENA
P1-B2
1
2
3
CD4001
U7
A
6
5
4
CD4001
U7
B
R3
470KΩ
R5
100KΩ
S
P
E
E
D
R6
100KΩ
MAX
C4
SEE TEXT
R
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
2
12
11
9
6
5
4
3
CD4024
U5
8
9
10
CD4081
U4
C
13
12
11
CD4081
U4
B
1
2
3
CD4071
U6
A
PDM_CLK
P1-5D
13
12
11
CD4071
U6
B
6
5
4
CD4071
U6
C
6
5
4
CD4081
U4
D
U3A_QN
P1-C3
U3A_Q
P1-C3
U3B_QN
P1-6D
R9
82KΩ
Q1
2N5400
+VDD
J1
KEY OUT
+VDD
S1
TUNE
+VDD
C6
0.001µF
+VDD
8
9
10
CD4001
U7
C
R7
470KΩ
R8
100KΩ
T
O
N
E
C5
0.01µF
13
12
11
CD4001
U7
D
8
9
10
CD4071
U6
D
R10
15KΩ
R11
100K
V
O
L
−VSS
Q2
2N4142
−VSS
SP1
+
-
B2
1.5V
+
−VSS
Mini-Mos Schematic, Page 3
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1
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1
A
B
C
D
A
B
C
D
Erich A. Pfeiffer, WA6EGY
Title
Power/Ground
Size
B
Document Number
73 Mag, Aug 1976
Rev
None
Date:
3/7/2020
Sheet 3 of 3
B1
9V
+
+VDD
−VSS
+
C3
22uF
VCC
GND
14
7
U1 - CD4011
VCC
GND
14
7
U2 - CD4081
VCC
GND
14
7
U3 - CD4013
VCC
GND
14
7
U4 - CD4081
VCC
GND
14
7
U5 - CD4024
VCC
GND
14
7
U6 - CD4071
VCC
GND
14
7
U7 - CD4001
Mini-Mos Timing, Page 1

This is a replica of the Timing Diagram, Fig. 5 from the original article. I replicated it because it's a little clearer and easier to read and the "T" time marking make it easier to see how one signal relates to another.

For the sending of the letter "T" (T1) and "E" (T7), the Dash and Dot paddles are closed (tapped) for a short amount of time. However, the sending of the letter "K" uses the Iambic properties of the keyer. The Dash paddle is closed first (T11) and then the Dot paddle is just tapped (T11-T12). A Dash is queued up first. Then a Dot is inserted when it is complete. Because the Dash paddle is held closed through the generation of the Dot, a final Dash is added. Completing the letter "K".

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1
A
B
C
D
A
B
C
D
Fig. 5. Pulse diagram showing the signals at different points of the circuit when the letters "-T-E-K-" are being sent.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T
E
K
DOT
CONTACT
CLOSED
OPEN
DASH
CONTACT
CLOSED
OPEN
U1A
U1C
U3A
SET
RESET
U3B
SET
RESET
U4C
Q7
Q6
Q5
U5
U7B
16
Q1
ON
OFF
Mini-MOS Updates - Mod. 1 - Chassis Ground for Paddle Common and Mod. 2 - Automatic Character Spacing

These are the modification from the March 1978 issue of 73 Magazine written by S. M. Allen, K4JEM. Rather than multiple small drawings I combined all of the mods into a single drawing.

Modification 1 deals with the common lead for your paddles. As originally designed, power is obtained from a 9 Volt Battery. The Positive side of the battery (+VDD) is connected to the VDD Input pin (14) on all IC's and Chassis Ground. The Negative side of the battery (-VSS) is connected to the VSS Input pin (7) on all IC's. This then requires the Dual Paddle Common to be at -VSS. (See the original drawing for page 1.) Should the Paddle Common, which is usually the paddle base, come in contact with your transmitters ground, the battery will be shorted.

This modification replaces the CD4011 Quad 2-Input NAND gate package, used in the Dual Paddle input circuit, with a CD4013 Dual D-Type Flip-Flop package. This allows the Dual Paddle input circuitry to be changed so that the Dual Paddle Common is at +VDD or Chassis Ground.

Referring to the schematic, the "Q" output, at U1A-1, goes to the input of U2A‑6 and U2B-8. But this is only true if Modification 2 is not installed. If Modification 2 is installed, U1A‑1 instead goes to U2A‑1 and U8A‑2. U2B is being reused in Modification 2.

Modification 2 adds Automatic Character Spacing to the list of features. And, the modifications is presented in two possible ways. In the first method, Mod. 2A shown below, an extras IC is added, U8 a CD4011 Quad NAND gate package. And, the Sidetone is eliminated and it's gates (U7C, U7C and U6D) are put to work as part of the Automatic Character Spacing modification. This modification also means the addition of U8 which is a CD4011 Quad NAND Gate package. All four gates in the package are used. The original article contains a reasonable good explanation of how it works.

Modification 2 can also be implemented without elimiating the Sidetone Generator, but would require adding two new ICs. U8 which is a CD4011 Quad NAND gate package and U9 which is a CD4001 Quad NOR gate package. The circuit may look a bit different, but it is functionally equivalent to Mod. 2A

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1
A
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C
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A
B
C
D
S. M. Allen, K4JEM
Title
Modifications 1, 2A, & 2B
Size
B
Document Number
73 Mag, Mar 1978
Rev
None
Date:
3/7/2020
Sheet 1 of 1
Paddle at Chassis
Ground - Mod. 1
DOT
PADDLE
+VDD
C1
1000pF
+VDD
R1
100KΩ
-VSS
S
R
D
Q
Q
3
5
6
4
1
2
CD4013
U1
A
-VSS
DASH
PADDLE
+VDD
C2
1000pF
+VDD
R2
100KΩ
-VSS
S
R
D
Q
Q
11
9
8
10
13
12
CD4013
U1
B
-VSS
U2A IN
U2B IN
OR U8A IN
U2C IN
U3A Q
U2C IN
U2D IN
U2A IN
U3B Q
Automatic Character Spacing Modification - Mod. 2 A
13
12
11
CD4011
U8
D
8
9
10
CD4011
U8
C
C7
10pF
‒VSS
R12
100KΩ
S2
AutoSpace
U4D-4
+VDD
8
9
10
CD4081
U2
B
8
9
10
CD4001
U7
C
13
12
11
CD4001
U7
D
U5-Q5
6
5
4
CD4011
U8
B
U3A Set In
1
2
3
CD4011
U8
A
U1A Out
OR U1A Q Out
U4A Out
8
9
10
CD4071
U6
D
U6C Out
U4D In
Automatic Character Spacing Modification - Mod. 2 B
13
12
11
CD4011
U8
D
8
9
10
CD4011
U8
C
C7
10pF
‒VSS
R12
100KΩ
S2
AutoSpace
U4D-4
+VDD
8
9
10
CD4081
U2
B
8
9
10
CD4001
U9
C
13
12
11
CD4001
U9
D
U5-Q5
6
5
4
CD4011
U8
B
U3A Set In
1
2
3
CD4011
U8
A
U1A Out
OR U1A Q Out
U4A Out
1
2
3
CD4001
U9
A
6
5
4
CD4001
U9
B
U6C Out
U4D In
Mini-MOS Update, S. M. Allen, K4JEM

What follows is another schematic of the Mini-MOS keyer but with the modifications indicated. Mod. 1 is shown in it's entirety. But it only shows the wires that need to be removed and the external connections for Mod. 2A and Mod. 2B. I didn't make a new schematic with Mod. 2A and Mod. 2B simply due to space issues. Plus, it would only create confusion with multiple copies of the schematic. Two different copies shouldn't be a problem. I did not bother a new Power/Ground schematic. There is really nothing different there except for the addition of Power/Ground for U8 and U9 and a change to U1.

The drawing shows Modification 1 enclosed in a dashed box. For Modification 2, the wires with "X" on them are removed and re-routed to the circled signal names.

Mini-Mos Update Schematic, Page 1
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1
A
B
C
D
A
B
C
D
S. M. Allen, K4JEM
Title
Mini-Mos with Modification 1 and 2
Size
B
Document Number
73 Mag, Mar 1978
Rev
None
Date:
3/7/2020
Sheet 1 of 3
DOT
PADDLE
+VDD
C1
1000pF
+VDD
R1
100KΩ
‒VSS
DASH
PADDLE
+VDD
C2
1000pF
+VDD
R2
100KΩ
‒VSS
S
R
D
Q
Q
3
5
6
4
1
2
CD4013
U1
A
-VSS
6
5
4
CD4081
U2
A
8
9
10
CD4081
U2
B
S
R
D
Q
Q
11
9
8
10
13
12
CD4013
U1
B
-VSS
1
2
3
CD4081
U2
C
13
12
11
CD4081
U2
D
S
R
D
Q
Q
3
5
6
4
1
2
CD4013
U3
A
-VSS
U3A_Q
P2-D6
U3A_QN
P2-6D
S
R
D
Q
Q
11
9
8
10
13
12
CD4013
U3
B
-VSS
U3B_QN
P2-6B
PDM_CLK
P2-4B
1
2
3
CD4081
U4
A
OSC_ENA
P2-A8
Modification 1
U2B reused in
Mod 2 A&B
Mod 2 - U8A-1
Mod 2 - U8B-4
Mod 2
U8A-2, U2B-9

For Modification 2, the wires with "X" on them are removed and re-routed to the circled signal names in the Mod 2A or Mod 2B schematic. If Mod 2A is used, which reuses the gates from the Sidetone Generator, remove the wires and components in the enclosed box.

Mini-Mos Update Schematic, Page 2
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A
B
C
D
A
B
C
D
S. M. Allen, K4JEM
Title
Page 2 Showing Modifications
Size
B
Document Number
73 Mag, Mar 1978
Rev
None
Date:
3/7/2020
Sheet 2 of 3
OSC_ENA
P1-B2
1
2
3
CD4001
U7
A
6
5
4
CD4001
U7
B
R3
470KΩ
R5
100KΩ
S
P
E
E
D
R6
100KΩ
MAX
C4
SEE TEXT
R
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
2
12
11
9
6
5
4
3
CD4024
U5
8
9
10
CD4081
U4
C
13
12
11
CD4081
U4
B
1
2
3
CD4071
U6
A
PDM_CLK
P1-5D
13
12
11
CD4071
U6
B
6
5
4
CD4071
U6
C
6
5
4
CD4081
U4
D
U3A_QN
P1-C3
U3A_Q
P1-C3
U3B_QN
P1-6D
R9
82KΩ
Q1
2N5400
+VDD
J1
KEY OUT
+VDD
S1
TUNE
+VDD
C6
0.001µF
+VDD
8
9
10
CD4001
U7
C
R7
470KΩ
R8
100KΩ
T
O
N
E
C5
0.01µF
13
12
11
CD4001
U7
D
8
9
10
CD4071
U6
D
R10
15KΩ
R11
100K
V
O
L
−VSS
Q2
2N4142
−VSS
SP1
+
-
B2
1.5V
+
−VSS
Mod 2 - U6D-8
Mod 2 - U4D-5
Mod 2 - U5-Q5
Mod 2 - S2_NC
Remove this section to use
U6D, U7C, & U7D in Mod 2A.
Retain this section for Mod 2B.