Introduction Drawing Definitions Symbol Options Symbol Test Bench Instantiation Code Fixes Lib Description

TTL Logic Symbols

The page is is a test bench for the symbols in the SN73xxx, SN74xxx, and SN75xxx TTL Logic library. The selectors provide the user with all possible options for each and every symbol. However, not all options apply to all symbols. You will see this when you select a logic device. The options listed below the Device Name will change dynamically, based on the specific device.

This page can also be used when you are drawing a logic schematic that contains TTL logic. Once you get the symbol you want in the test area, and adjusted with the proper annotation, the complete instance is available below the selection area. This code can then be inserted directly into your drawing script. There will be a few things, like the Drawing Object and Symbol Coordinates, that need changing. But the rest can just be used as is.

This is not a comprehensive library of TTL logic devices. I started with a basic set of gates and then only add more complex devices as I find the need for them. For information on how to add a symbol to the library, see the section at the botton of this page labeled Adding a Symbol to the Logic Library

Note that, for logic gates, there are no options for rotating a logic symbol, so that it would face up, down, or backwards. I originally had that capability but removed it. I personally never use rotated logic symbols and found that including that capability only serves to over complicate the source code. It just isn't worth the extra code to provide this capability. A good designer can figure a way around rotated logic symbols.

An exception to this are some larger ICs that have only one section. These are higher level functions, like counters or shift registers. These ICs have the ability to be displayed vertically or hrorizontally.

One option that I did retains is the use of DeMorgan equivalents. Since DeMorgan equivalents are really only needed for gated, I thought they should be retained.

Introduction Drawing Definitions Symbol Options Symbol Test Bench Instantiation Code Fixes Lib Description

Drawing Definition

To draw a symbol, you first need a place to draw the symbol. I use a <div>...<div> structure to contain the drawing. The drawing area can be styled to whatever dimension suites you. I mostly use a style class called "B-Size". This is a drawing area that is 900 pixels wide and 600 pixels high. The upper left corner is considered (0,0). The drawing structure also needs a id. The id makes the drawing structure unique and is used by the draw program to address the correct drawing. Within the drawing, the id is the TTL_Obj.

An example of the code that you can put into a HTML file, so you can draw a picture, is below. The example definces a space that is "B-Size" (900 x 600 pixels), has a 1 pixel solid green border, and is named "My_Schematic". The definition for the "B-Size" class is in the master CSS file.

<div id="My_Schematic" class="B-Size" style="border: solid 1px green;"><div>

Other definitions that can be added to the "style" are "margin" and "float". You could even included height and width if you want to start with a larger drawing area and then pare down when it's completed. But that brings up another issue on how to group your drawing symbols so that the drawing area can be reduced.

Introduction Drawing Definitions Symbol Options Symbol Test Bench Instantiation Code Fixes Lib Description

Symbol Options

An example of a call to draw a logic symbol is below.

TTL_Return[] = TTL_Logic( TTL_Obj, TTL_RefDes, TTL_Dev, TTL_Opt, TTL_Sect/TTL_MapTo, Center_X, Center_Y );

In some special cases, like including the resistor and capacitor for a SN74121 and SN74122 Mono-Stable, the call to draw a logic symbol might look like this:

Lib_TTL_RC_Array = [ "R1","10K","C1",".01 uF" ];
TTL_Return[] = TTL_Logic( TTL_Obj, TTL_RefDes, TTL_Dev, TTL_Opt, TTL_Sect-TTL_MapTo, Center_X, Center_Y );

The Javascript command above, draws a TTL symbol starting at point Center_X, Center_Y. TTL_Return[] is an array of coordinates for the input, output, and control signals that a particular device may have. Where:

• TTL_Obj - Drawing Object or id. This is the id of the <div>...<div> structure that you defined, in the HTML file, to contain the drawing.
• TTL_RefDes - Reference Designator. Every symbol on a schematic has a unique name, or Reference Designator, that identifies the specific device (e.g. "U1" through "U20)
• TTL_Dev - This is the name of the logic device that you want to draw. See the TTL_Dev dropdown for a list of available devices.
Normal/DeMorgan | Reserved | | NoSwap/Swap | | | Technology | | | S LS F H HC HCT C | | | | | | | | | | | | | | | | | | | | Bit 0 1 2 3 4 5 6 7 8 9 VAL 1 2 4 8 16 32 64 128 256 512 Example: Normal | NoSwap = 0 Example: DeMorgan | Swap = 4 | 1 = 5 Example: DeMorgan | NoSwap = 1 Example: Normal | NoSwap | HCT = 256
• TTL_Opt - This is a number between 0 and 517 that indicates the options that are to be applied to this symbol. The selections listed below are "ORed" together to obtain the TTL_Opt value.
• TTL_DeMorgan = 1 - This option displays the DeMorgan Equivalent of the logic symbol defined in TTL_Dev. Note that only gates have a DeMorgan Equivalent
• TTL_Swap = 4 - When replicating a drawing it common for the input pin ordering to not match the original. This option allows for the swapping of input pins. For logic gates with only two inputs, this operation is relatively simple. When set Lib_S_Swap will switch the input pin numbers. However, for gates with more than two inputs, this is a fairly complex operation. That's because a SN7410, with 3 inputs, has 6 possibilities and a SN7420, with 4 inputs, has 24 possibilities. But, when you are working with a SN7430, with 8 inputs, the number of possibilities is 40,320. Even further is the SN74133 with 13 inputs. The swap possibilities are over 6 billion. That's a little bit more than I want to deal with.
• TTL_Technology = S=8 | LS=16 | F=32 | H=64 | HC=128 | HCT=256 | C=512 - To specify a logic device's specific technology, a group of 1 to 3 letters are inserted between the SN74 and the logic device's ID number. So a Standard TTL logic device might be a SN7400, but a Low Powered Schottky logic device would be specified as SN74LS74.
• TTL_Sect-TTL_MapTo -
• Center_X, Center_Y -

Introduction Drawing Definitions Symbol Options Symbol Test Bench Instantiation Code Fixes Lib Description

TTL Test Bench

Parameter	Description		Example
Dwg_Obj	jsGraphics Object that points to the drawing.		0 10 30 50 70 90 110 140 170 320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 B↓ A↓ R01 R02 QD QC QB QA 14 1 6 7 8 9 11 12 S N 7 4 9 2 U 1
TTL_RefDes	Reference Designator ("U1", "U2", etc.) quoted string. U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 none
TTL_Dev	Device Name ("SN7400", "SN7402", etc.) quoted sting. OC = Open Collector. MAX232 - RS232 Interface SN7302 - Dual JK-Flop w/Preset SN7360 - Quad 2-Input NAND Gate SN7400 - Quad 2-Input NAND Gate SN7401 - Quad 2-Input NAND Gate (OC) SN7402 - Quad 2-Input NOR Gate SN7404 - Hex Inverter SN7405 - Hex Inverter (OC) SN7406 - Hex Inverter (HVOC) SN7407 - Hex Buffer (30V-OC) SN7408 - Quad 2-Input AND Gate SN7410 - Triple 3-Input NAND Gate SN7411 - Triple 3-Input AND Gate SN7413 - Dual 4-Input NAND Gate (Schmidt) SN7417 - Hex Buffer (15V-OC) SN7420 - Dual 4-Input NAND Gate SN7421 - Dual 4-Input AND Gate SN7430 - 8-Input NAND Gate SN7432 - Quad 2-Input OR Gate SN7447 - BCD to 7-Seg Dec SN7473 - Dual M/S JK-Flop w/R SN7473A - Dual JK-Flop w/R SN7474 - Dual D-Flop w/RS SN7475 - 4-Bit Bistable Latch SN7476 - Dual JK-Flop w/RS SN7490 - Counter, Decade SN7492 - Counter, Div 12 SN7493 - Counter, Binary SN74112 - Dual JK-Flop w/RS SN74121 - Monostable, Retrig SN74123 - Dual Monostable, Retrig SN74132 - Quad 2-Input NAND Gate SN74138 - 3 To 8 Decoder/Demux SN74151 - Data Selector/Mux, 1 of 8 SN74160 - Counter, Synch Decade SN74161 - Counter, Synch Decade SN74162 - Counter, Full Synch 4-Bit Binary SN74163 - Counter, Full Synch 4-Bit Binary SN74193 - Synchronous 4-Bit Up/Down Counter SN74194 - Shift Reg, 4-Bit Bi-Directional SN74221 - Dual Monostable, Retrig SN74240 - TS Inv Octal Buffer SN74241 - TS Octal Buffer SN74273 - Octal D-FF W/Clear SN75154 - Quad Line Receiver, INV SN75451 - Dual Hi-I/Hi-Speed Driver, AND SN75452 - Dual Hi-I/Hi-Speed Driver, NAND SN75453 - Dual Hi-I/Hi-Speed Driver, OR SN75454 - Dual Hi-I/Hi-Speed Driver, NOR
TTL_Opt	Normal DeMorgan Right Left None S LS F H HC HCT C No Swap Swap Pin Order
TTL_Sect	Body  PWR
TTL_MapTo	Use TTL_Sect Pins but use TTL_MapTo label A
TTL_RC	For SN74121, SN74123 Mono-Stables Only → No R/C Show R/C R-Refdes R-Value C-Refdes C-Value
Center_X	Symbol Center X Position	Show/Hide Grid (10x10), Center Mark (Orange), Pins (purple dot). Grid On Off Center On Off Pins On Off
Center_Y	Symbol Center Y Position

Introduction Drawing Definitions Symbol Options Symbol Test Bench Instantiation Code Fixes Lib Description

Instantiation Code

The selections from the Test Bench above, are used to create the example code below. After selecting and entering your specific information in the Test Bench, the code below can be used directly, with a copy/paste. The items in Red are the only ones that need to be adjusted to your specific needs. The lines in Green are just comments and can be deleted. Due to space limitations, some of the lines below may be split onto more than one line.

Note: In the instantiation code above, the return value from the call to TTL_Logic(); is an array of X-Y coordinates that match the signal pins shown in the Test Bench above.

Introduction Drawing Definitions Symbol Options Symbol Test Bench Instantiation Code Fixes Lib Description

Fixes Required for the TTL Library

These are items that are still outstanding in the TTL Library. When they are fixed, they will be removed.

• The 7490 and 7493 need rotated versions (90 degrees CCW).
• The 74138 needs rotated versions (90 degrees CCW).
• The 7475 mostly works. But:
  • When the AB Vertical display is selected, var U1AB_Option_Val = Lib_TTL_Left; is added to the Instantiation code. This needs to be changed to var U1AB_Option_Val = Lib_TTL_Vert;. Fixed
  • Remove the U1AB from the Instantiation code. It should only say U1. Fixed
• Add the ability to rotate some of the higher order functions (e.g. counters, latches, etc.) 90 degrees, so that their inputs are at the botton and outputs at the top.
  • Change the test bench to read Horiz/Vert instead of Right/Left. The selection return will be the same for Horiz/Vert and Right/Left but will only apply to specific devices.
  • Also need to change the U1AB_Option_Val = Lib_TTL_Left; to read U1AB_Option_Val = Lib_TTL_Vert;.
  • Remove the U1AB from the Instantiation code. It should only say U1.

Introduction Drawing Definitions Symbol Options Symbol Test Bench Instantiation Code Fixes Lib Description

Logic Symbol Library Description

The structure of the TTL Logic Library is relatively simple. Each and every symbol is drawn in the same manner. As seen in the flow chart, upon entry an association with a Device Array is established (P1). Each device has a separate array that defines all of the pins. The first number in the array defines the number of pins. This is then followed by a list of pins. The order of the pins generally follows the section order. If the logic device has only one section, the order generally lists inputs first, than outputs. If the logic device has multiple sections, the input and output pins are grouped by section.

Once the Device Array is established (P1), a check is made to see if we are only drawing the Power/Ground pins (D1). If Power/Ground is specified, the Power/Ground symbol is drawn (P2), Pin Numbers (P5) are added, a Device Name (P6) is added, and a Reference Designator (P7) is added.

If Power/Ground is not specified, then a Section is usually specified. The Section is usually a simple "A", "B", "C" etc.. But a Section label is not consistant across all schematics. One designer may consider a particular pin group to be Section A. Whereas, someone else might label the same pin group as Section B. It's not a big deal, except when you are trying replicate the drawing. So it is often possible to see a Section specification as "A-C". In this library, that means draw the symbol with pin numbers from pin group "A", but label it as section "C". A very useful capability.

The next step in the flow chart, if Power/Ground is not specified, is to draw the symbol. If the symbol is a gate, there is the option of simply drawing the standard gate symbol, or the Demorgan Equivalent of the gate can be used. If you don't know what a Demorgan Equivalent is, or why it is used, look it up. If it isn't a gate, then the common logic symbol, for that device, is drawn.

Once the logic symbol is drawn, the pin numbers, device name, and reference designator are added to the symbol and a X-Y Coordinate Array is returned to the calling routine. The X-Y Coordinate Array contains the X and Y coordinated of each input, output, and control pin, in pixels referenced to 0,0 on the drawing. For all of my drawings, 0,0 is at the bottom left of the drawing area.

For the most part, all symbols are drawn in the same manner. In many cases, the same code is used to draw several similar logic symbols. For example, the "SN7402" and "SN7432" are similar. They both have a 2-Input OR body. The only difference is that the "SN7402" has an inverted output (bubbled). Whereas, the "SN7432" does not. So, the same code is used for drawing both logic symbols, until the output is drawn. At that point there is a few lines of code that will draw either a bubbled output or wire output, depending on the logic device. This cuts down on the amount of code needed for the library.