Introduction

This is just a sampling of audio circuits that I have found useful and interesting.

Digital Volume Control

Below is the circuit diagram of stereo digital volume control. In this circuit, switch S1 controls increasing the volume and switch S2 controls decreasing the volume.

DIS
THR
TRI
GND
RST
VCC
OUT
CTL
8
1
7
6
2
4
3
5
U1
ICM7555
+5V
+5V
R1
150 KΩ
+5V
R2
330 KΩ
+
C1
1 µF
C2
0.1 µF
S1
Up
S2
Down
R3
560 Ω
+5V
R4
560 Ω
+5V
S3
RST
+5V
R5
560 Ω
A
B
C
D
UP↑
DN↑
LD
CLR
QA
QB
QC
QD
CO
BO
15
1
10
9
5
4
11
14
3
2
6
7
12
13
SN74193
U2
+
5
V
QA
QB
QC
QD
VCC
GND
16
8
U2 - SN74193
+5V
VCC
GND
14
7
U3 - CD4066
+5V
VCC
GND
14
7
U4 - CD4066
+5V
J1
Left In
13
1
2
CD4066
U3-A
QA
R6
1 KΩ
5
4
3
CD4066
U3-B
QB
R7
2 KΩ
6
8
9
CD4066
U3-C
QC
R8
4.7 KΩ
12
11
10
CD4066
U3-D
QD
R9
8.2 KΩ
R14
4.7 KΩ
J2
Left Out
J3
Right In
13
1
2
CD4066
U4-A
QA
R10
1 KΩ
5
4
3
CD4066
U4-B
QB
R11
2 KΩ
6
8
9
CD4066
U4-C
QC
R12
4.7 KΩ
12
11
10
CD4066
U4-D
QD
R13
8.2 KΩ
R15
4.7 KΩ
J4
Right Out

The IC1 timer, ICM7555, is set up as an astable multivibrator and generates low-frequency pulses to the up/down clock input pins of the 74LS193 (IC2) up/down counter, through switches S1 and S2. The pulse frequency can be controlled by changing the value of R1 on IC1.

Operation of switch S1 (up) triggers the binary output to increment while operation of S2 (down) triggers the binary output to decrement. The highest count being 15 (all outputs logic 1) and lowest count being 0 (all outputs logic 0), it outcomes in highest and lowest volume respectively.

The active high outputs A, B, C and D of the counter (IC2) are utilized to controll two quad bi-polar analogue switches, CD4066 ICs (IC3 and IC4). Each switch section shorts part of the resistor network comprising series resistors R6 thru R9, for one channel, and R10 thru R13, for the other channel. Switch S3 is utilized for resetting the output of counter to 0000. This sets the volume of both channels to the lowest level.

This circuit is really only meant as an idea, because there are some drawbacks.

  • First, there is no debounce on the switches. This can cause erratic changes in the volume. It might be better to have two timers configured as mono-stable oscillators, each triggered by a separate switch. One for counting up, the other for counting down. A dual timer could be used.
  • Second, there is no count limit control. When counting up or down, the counter can readily change from minimum (0000) to maximum (1111), or visa versa, with a single switch push. You could probably use the Carry (CO) and Borrow (BO), to gate out pulses when minimum or maximum count is encountered.

Dynamic Microphone Preamps
J1
Mike In
+
C1
2.2 uF/6V
R1
470 Ω
R2
10-47 KΩ
Q1
BC549C
R3
47 KΩ
R4
12 KΩ
+
C2
47 uF/16V
+12V
C3
0.47 uF
10.5V
Q2
BC547B
R5
820 Ω
R6
100 Ω
R7
1 KΩ
+
C4
2.2 uF/6V
5.2V
R8
100 KΩ
J2
Audio Out

Dynamic microphones are also better suited to handling high volume levels, such as from certain musical instruments or amplifiers. They have no internal amplifier and do not require batteries or external power.

This dynamic microphone amplifier circuit has a total gain of about 200 X. If you use 200Ω microphones, R1 should be 220Ω and C1 should be 4.7µF. For the best performance, use metal film resistors, MKM type for unpolar capacitor and tantalum type for bipolar capacitor. Use a stable, regulated, power supply. With a 3mV (P-P) input signal, the output will be 800m (P-P). The maximum output voltage is about 10V (P-P), when the input is 50mV (P-P). The bandwidth is from 50Hz to 100KHz.


VCC
6-30V
D1
1N4148
R2
100 Ω
+
C1
470 uF/25V
R1
15 KΩ
+
C2
4.7 uF/25V
R3
2.2 KΩ
R4
150 KΩ
Q1
2N1234
J1
Low Imp
+
C3
22 uF/25V
R5
820 Ω
C4
0.1 uF
High Imp
R6
3.9 KΩ
+
C7
100 uF/25V
R7
10 KΩ
R8
10 KΩ
+
C5
10 uF/25V
+
U1
TL081
V+
V-
7
4
2
3
6
R9
1 MΩ
C6
47 uF
J2
Out

This is the diagram of a Low Impedance (~200 ohm) microphone amplifier. It can be powered with 6-30 VDC. The input section, consisting of R1, R3, R4, R5, C1, and C2, is a grounded base Low-to-High Impedance Matching circuit. If you are working with a High Impedance microphone, or High Impedance audio source, the input section can be eliminated and the audio input at C4 (as shown on the diagram).

R7 and R8 form a voltage divider that keeps the plus input of the op-Amp at 1/2 the supply voltage. C5 stabilized this voltage. R9 sets the Gain of the High Impedance Op-Amp stage. At the low end, stage gain will be around 1 (0 dB). At the high end, stage gain will be around 250 (~24 dB).

Audio Booster
J1
Input
+
C1
0.1 uF/25V
R1
470 KΩ
R2
47 KΩ
Q1
2N3392
R3
10 KΩ
R4
560 Ω
+
C2
3.3 uF/25V
+
C3
470 uF/25V
R5
100 KO Ω
J2
Out
+9V

This is a pretty simple circuit for in front of a power amplifier. This small amplifier circuit has a maximum gain of around 22 dB (voltage gain) and the frequency response is +/-3.0 dB from about 120 Hz to higher than 20,000 Hz. The low frequency response is determined primarily by the value of C1 and R2.

Rin = RS+(R1//R2//ßRE) = 500 + ( 80K // 30K // 100*25 ) = 20.2 kΩ
fcl,in = 1/(2*PI*Rin*C1) = 1/(6.28*21.2E3*0.1e-6) = 75.1 Hz

Rin = RS+(R1//R2//ßRE) = 0 + ( 470K // 47K // 100*25 ) = 20.2 kΩ.
fcl,in = 1/(2*PI*Rin*C1) = 1/(6.28*47E3*0.1e-6) = 34 Hz

With R1 being fixed, the low frequency roll-off is controlled by capacitor C1. If the value of C1 ischanged to 0.1 pF, the low end’s comer frequency - the frequency at which the low-end roll-off starts - is decreased to about 70 Hz. Should you need an even deeper low-end roll-off, modify C1 to a 1.0 pF capacitor; if it is an electrolytic type, make certain that it is installed into the circuit together with the appropriate polarity, with the positive terminal linked to the base of Q1.